Chapter 2: Important ISE Design Suite 13 Release Information
The PlanAhead workspace views are redesigned with an auto-fit selection. A drop-
down in the Main toolbar lets you select applicable views for the open Project. The
workspace views now contain dock/undock, float, minimize/maximize, and restore
buttons.
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Search Option
PlanAhead has added a search text box on the main menu to search through all the
menu options for the specified text.
Export Options
A new option in the PlanAhead File >Export > Export IBIS Model is available in an
open design. The Input/Output Buffer Information Specification (IBIS) is used analyze
the design. The IBIS model exported from PlanAhead is compliant with the IBIS
version 4.2, and uses the defaults of that specification.
Single Click Implementation
PlanAhead now allows you to click on the Implementation button in the flow
navigator and the tool will launch a dialog prompting if you want to launch synthesis
first if you have an RTL project, and the synthesis run is out of date. This allows you to
do “one-click” implementation of RTL. This feature requires that you have PlanAhead
in GUI mode – if you close the project, only the currently running Synthesis run
completes: the Implementation run does not launch.
Source View Enhancements
The PlanAhead release 13 provides enhanced views for source file structures and
editing.
Third Party Text Editor Support
PlanAhead now allows the ability to use third-party editors for editing source code
files.
Message Manager
A new Messages view consolidates error, critical warning, warning, and informational
messages from PlanAhead and ISE point tools into a single view. Messages are linked
to the source code to allow for quick exploration and resolution of any errors or
warnings.
Netlist View Additions and Modifications
The following subsections describe the additions and modifications to the PlanAhead
Netlist view.
Clocking Resource View
The new Clocking Resource view available in the PlanAhead GUI aids in the
visualization and assignment of clocking-related sites and physical resources within
the FPGA.
Folders for Component Switching Limits
There are new folders in the timing results view imported from TRCE that better
organize the component pin switching limit violations with setup and hold violations.
The violations are sorted and the worst violation is displayed first within a constraint.
Enhanced Slack Histogram Report
PlanAhead release 13 contains an improved slack histogram feature which creates a
graphical bar chart corresponding to collections of paths within ranges from most
negative to most positive.
22
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.1)
相关PDF资料
EF-EDK-FL SOFTWARE EDK EMBED FLOAT
EF-ISE-DSP-FL SOFTWARE ISE DSP EDITION
EF-ISE-SYSTEM-FL ISE DESIGN SYST FLOATING LICENSE
EF-VIVADO-HLS-FL VIVADO HLS, FLOATING LICENSE
EFM32-GXXX-PTB BOARD PROTOTYPING FOR EFM32
EFS315 FUSE INDUST 315A 415V BS IEC
EHBNCSCB CONN EH BNC T/H SOLDER CUP BLK
EHE004 BOARD ENERGY HARVESTING
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EF-DSP-PC-NL 功能描述:SOFTWARE SYS GEN FOR DSP RoHS:是 类别:编程器,开发系统 >> 软件 系列:ISE® 设计套件 标准包装:1 系列:ISE® 设计套件 类型:订阅 适用于相关产品:Xilinx FPGAs 其它名称:Q4986209T1081384
EFDSS645B25A 制造商:Panasonic Industrial Company 功能描述:DELAY LINE
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EFE01B 制造商:CRYDOM 制造商全称:Crydom Inc., 功能描述:Power Modules